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Design of Digital PLL/CDR with Advanced Digital Controller : 진보된 디지털 컨트롤러를 이용한 디지털 위상 동기화 루프와 클럭 및 데이터 복원 회로의 설계
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 김재하 | - |
dc.contributor.author | 류시강 | - |
dc.date.accessioned | 2017-07-14T02:55:10Z | - |
dc.date.available | 2017-07-14T02:55:10Z | - |
dc.date.issued | 2014-02 | - |
dc.identifier.other | 000000018062 | - |
dc.identifier.uri | https://hdl.handle.net/10371/123053 | - |
dc.description | 학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 김재하. | - |
dc.description.abstract | This paper presents a design methodology of digital PLL/CDR with various digital controllers. In comparison with analog approaches, digital techniques can circumvent inherent design constraints of analog-based timing circuits, thereby achieve such as non-linear transfer, gear shifting (adaptive damping technique), fast-locking algorithm and so on.
First, this paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is, the PLLs second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs, the proposed PLL implements the peaking-free loop filter directly in digital domain without requiring additional components. A time-to-digital converter (TDC) is implemented as, a set of three binary phase-frequency detectors that oversample the timing error with time-varying offsets, achieving a linear TDC gain and PLL bandwidth insensitive to the jitter condition. And a 9.2-GHz digitally-controlled LC oscillator (DCO) with transformer-based tuning realizes a predictable DCO gain set by a ratio between two digitally-controlled currents. The prototype 9.2-GHz-output digital PLL fabricated in a 65nm CMOS demonstrates a fast settling time of 1.58-μs with 690-kHz bandwidth. The PLL has a 3.477-psrms divided clock jitter and -120dBc/Hz phase noise at 10-MHz offset while dissipating 63.9-mW at a 1.2-V supply. Second, the proposed high-order clock and data recovery(CDR) employs tracking aid to track frequency modulated data using spread-spectrum clocking(SSC) to mitigate steady-state jitter characteristic. This paper describes the implementation of the tracking aid to achieve accurate estimation of the time instants. Instead of the noise sensitive differentiator used in previous works, the proposed architecture uses an integrator that is more resilient to noise or disturbance and more accurate. The design of the architecture fully implemented in digital achieves SSC timing errors less than < 10 cycles, locking time < 15 ms overall CDR jitter of 0.12UIpp. | - |
dc.description.tableofcontents | 1. Introduction 1
1.1 Digital PLL/CDR 1 1.2 Thesis Organization 3 2. Digital Phase-Locked Loop with Peaking-free Transfer Function 2.1 Introduction of Peaking-Free Digital PLL 4 2.2 Peaking-Free Digital PLL Architecture 6 2.2.1 Jitter Peaking in Conventional Second-Order PLLs 6 2.2.2 Previously Reported Peaking-Free PLLs 8 2.2.3 The Proposed Peaking-Free Digital PLL 12 2.3 Analysis on Peaking-Free Digital PLL Dynamics 14 2.3.1 Case Without High-Pass Filter 15 2.3.2 Case With High-Pass Filter 18 2.4 Circuit Implementation 23 2.5 Measurement Results 34 3. A Noise-Resilient Tracking Aid for Digital Clock and Data Recovery of Spread-Spectrum Clocked (SSC) Signal 40 3.1 Introduction of SSC tracking CDR 40 3.2 SSC Tracking Architecture 43 3.2.1 Conventional Architecture 43 3.2.2 Concept of Integration-based SSC Tracking Loop 47 3.3 CDR Archtecture with SSC Tracking Loop 52 3.3.1 SSC Tracking Loop 52 3.3.2 Trade-offs among Parameters 60 3.3.3 Additional SSC Tracking Aid 63 3.3.4 Overall CDR Architecture 66 3.4 Simulated Results 72 4. Conclusion 74 Bibliography 76 Abstract (Korean) 80 | - |
dc.format | application/pdf | - |
dc.format.extent | 2558491 bytes | - |
dc.format.medium | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | 서울대학교 대학원 | - |
dc.subject | PLL | - |
dc.subject | CDR | - |
dc.subject | Digital loop filter | - |
dc.subject | digital controller | - |
dc.subject | digital PLL | - |
dc.subject | digital CDR | - |
dc.subject | TDC | - |
dc.subject | BBPFD | - |
dc.subject | Transfer function | - |
dc.subject.ddc | 621 | - |
dc.title | Design of Digital PLL/CDR with Advanced Digital Controller | - |
dc.title.alternative | 진보된 디지털 컨트롤러를 이용한 디지털 위상 동기화 루프와 클럭 및 데이터 복원 회로의 설계 | - |
dc.type | Thesis | - |
dc.description.degree | Master | - |
dc.citation.pages | vii, 81 | - |
dc.contributor.affiliation | 공과대학 전기·컴퓨터공학부 | - |
dc.date.awarded | 2014-02 | - |
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