Cost-effective Hardware Design of a SPIHT Compression Algorithm

Abstract

Set Partitioning In Hierarchical Trees (SPIHT) is one of most popular embedded coding algorithms applied for wavelet coding images. It allows progressive transmission of information and gives high coding efficiency. In addition, it can omit entropy coding of the bit stream by arithmetic code with only small loss in performance. Thus it offers a cheaper and faster hardware design. In this dissertation, a cost-effective design of a SPIHT-based algorithm is proposed. In this algorithm, an image is partitioned into 1x64 blocks, each of which is transformed by DWT to generate wavelet coefficients. The wavelet coefficients are coded by SPIHT to generate bit-stream. Due to the mismatch of the data structure between DWT and SPIHT, the large buffers are required. In order to reduce buffers, a new data structure of wavelet coefficients and partitioned SPIHT are proposed. A wavelet-based block is partitioned into small sub-blocks each of which is compressed independently. To minimize distortion due to the sub-block-based compression, a bit-allocation scheme is proposed. The proposed design is implemented in both software and hardware. Experimental results show that the proposed design reduces the buffer size while minimizing the degradation of the rate-distortion performance. It is proved that the proposed design outperforms previous designs in hardware cost.