Implementation and Improvement of a Swing Modulo Scheduler for VLIW Architecture

Abstract

For VLIW architectures, compiler is in charge of statically scheduling instructions since there are no hardware for hazard detection in this kind of architecture. Thus, instruction scheduling techniques for VLIW architectures have critical influences on both correctness of parallel executions and effective utilization of hardware resources. Software pipelining is one of the popular instruction scheduling techniques which enables overlapped execution of successive loop iterations. We implemented a module of compiler, a swing modulo scheduler, to achieve software pipelining for target VLIW architecture. Experiments on a set of multi-media applications show that with swing modulo scheduler, it has up to 2.6 times speed-up in performance when comparing to the basic list scheduling implementation.