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Implementation and Improvement of a Swing Modulo Scheduler for VLIW Architecture
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 백윤흥 | - |
dc.contributor.author | 정현균 | - |
dc.date.accessioned | 2017-07-14T03:02:06Z | - |
dc.date.available | 2017-07-14T03:02:06Z | - |
dc.date.issued | 2015-08 | - |
dc.identifier.other | 000000067237 | - |
dc.identifier.uri | https://hdl.handle.net/10371/123194 | - |
dc.description | 학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 8. 백윤흥. | - |
dc.description.abstract | For VLIW architectures, compiler is in charge of statically scheduling instructions since there are no hardware for hazard detection in this kind of architecture. Thus, instruction scheduling techniques for VLIW architectures have critical influences on both correctness of parallel executions and effective utilization of hardware resources. Software pipelining is one of the popular instruction scheduling techniques which enables overlapped execution of successive loop iterations. We implemented a module of compiler, a swing modulo scheduler, to achieve software pipelining for target VLIW architecture. Experiments on a set of multi-media applications show that with swing modulo scheduler, it has up to 2.6 times speed-up in performance when comparing to the basic list scheduling implementation. | - |
dc.description.tableofcontents | 1. Introduction………………………………………………………………………………………. 1
2. Background……………………………………………………………………………………….. 3 2. 1 Very Long Instruction Word (VLIW) Architecture…………………………………… 3 2. 2 Instruction Scheduling for VLIW Architecture………………………………………… 4 2. 3 Software Pipelining for VLIW Architecture…………………………………………….. 5 2. 4 LLVM Compiler Infrastructure……………………………………………………………….. 6 3. Swing Modulo Scheduling………………………………………………………………….. 8 3.1 Build Data Dependence Graphs……………………………………………………………… 8 3.2 Calculate Minimum Initiation Interval (MII)……………………………………………. 9 3.3 Analysis and Computation………………………………………………………………….... 10 3.4 Order Nodes…………………………………………………………………………………………. 11 3.5 Schedule Nodes……………………………………………………………………………………. 12 4. Implementation and Improvement……………………………………………………13 4.1 Preprocess Basic Blocks………………………………………………………………………… 13 4.2 Build Scheduling Graphs……………………………………………………………………….. 14 4.3 Find or Build Basic Induction Variables…………………………………………………. 15 4.4 Calculate Resource MII…………………………………………………………………………. 16 4.5 Find All Circuits for Calculating Recurrence MII…………………………………….. 17 4.6 Break Anti-dependences………………………………………………………………………. 19 4.7 Compute Partial Order…………………………………………………………………………. 20 4.8 Compute Final Order……………………………………………………………………………. 21 4.9 Construct Prologue, Kernel and Epilogue……………………………………………… 22 4.10 Check Register Pressure……………………………………………………………………… 23 4.11 Adjust Loop Iteration Count……………………………………………………………….. 23 5. Experimental Results…………………………………………………………………………25 5.1 Environment………………………………………………………………………………………... 25 5.2 Performance………………………………………………………………………………………… 26 5.3 Effectiveness………………………………………………………………………………………… 27 6. Conclusion and Future Work……………………………………………………………..29 Reference……………………………………………………………………………………………..30 | - |
dc.format | application/pdf | - |
dc.format.extent | 1124915 bytes | - |
dc.format.medium | application/pdf | - |
dc.language.iso | ja | - |
dc.publisher | 서울대학교 대학원 | - |
dc.subject | VLIW architecture | - |
dc.subject | swing modulo scheduling | - |
dc.subject.ddc | 621 | - |
dc.title | Implementation and Improvement of a Swing Modulo Scheduler for VLIW Architecture | - |
dc.type | Thesis | - |
dc.description.degree | Master | - |
dc.citation.pages | iii, 31 | - |
dc.contributor.affiliation | 공과대학 전기·컴퓨터공학부 | - |
dc.date.awarded | 2015-08 | - |
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