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Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hyungjin | - |
dc.contributor.author | Lee, Jong-Ho | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.creator | 박병국 | - |
dc.date.accessioned | 2018-01-24T05:59:56Z | - |
dc.date.available | 2020-04-05T05:59:56Z | - |
dc.date.created | 2018-09-06 | - |
dc.date.created | 2018-09-06 | - |
dc.date.created | 2018-09-06 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.citation | Applied Physics Express, Vol.9 No.8, pp.084201-084201 | - |
dc.identifier.issn | 1882-0778 | - |
dc.identifier.uri | https://hdl.handle.net/10371/139008 | - |
dc.description.abstract | One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention time. In this letter, a 1T-DRAM cell with two separated asymmetric gates was fabricated and evaluated to improve sensing margin and retention characteristics. It was observed that significantly enhanced sensing margin and retention time over 1 s were obtained using a negatively biased second gate and trapped electrons in the nitride layer because of increased hole capacity in the floating body. These findings indicate that the proposed device could serve as a promising candidate for overcoming retention issues of 1T-DRAM cells. (C) 2016 The Japan Society of Applied Physics | - |
dc.language | 영어 | - |
dc.language.iso | en | en |
dc.publisher | Japan Soc of Applied Physics | - |
dc.title | Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement | - |
dc.type | Article | - |
dc.identifier.doi | 10.7567/APEX.9.084201 | - |
dc.citation.journaltitle | Applied Physics Express | - |
dc.identifier.wosid | 000383983200023 | - |
dc.identifier.scopusid | 2-s2.0-84981332766 | - |
dc.description.srnd | OAIID:RECH_ACHV_DSTSH_NO:T201633481 | - |
dc.description.srnd | RECH_ACHV_FG:RR00200001 | - |
dc.description.srnd | ADJUST_YN: | - |
dc.description.srnd | EMP_ID:A001741 | - |
dc.description.srnd | CITE_RATE:2.667 | - |
dc.description.srnd | DEPT_NM:전기·정보공학부 | - |
dc.description.srnd | EMAIL:bgpark@snu.ac.kr | - |
dc.description.srnd | SCOPUS_YN:Y | - |
dc.citation.endpage | 084201 | - |
dc.citation.number | 8 | - |
dc.citation.startpage | 084201 | - |
dc.citation.volume | 9 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Lee, Jong-Ho | - |
dc.contributor.affiliatedAuthor | Park, Byung-Gook | - |
dc.identifier.srnd | T201633481 | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | 1T-DRAM CELL | - |
dc.subject.keywordPlus | 1T DRAM | - |
dc.subject.keywordPlus | UTBOX | - |
dc.subject.keywordPlus | BODY | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | SOI | - |
dc.subject.keywordPlus | TIME | - |
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