Design Methodologies using Multi-bit Flip-flops for Low Power

Abstract

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this dissertation, a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF) is introduced. The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart, providing no need to set aside white space (i.e., no relocation) and relaxed timing check requirement. Utilizing LC-MBFFs, an multi-bit flip-flop allocation algorithm considering the routability and the clock tree, which fully explores the diverse allocation of LC-MBFF structures is also proposed to maximally reduce clock power consumption. Additionally, the proposed algorithm is extended to efficiently support the multi-bit flip-flop allocation for circuits with clock polarity assignment. Clock polarity assignment is a technique to mitigate power/ground noise by assigning different clock polarities to clock buffers. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that the proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power consumed in the flip-flops by 8.51% on average while the best known multi-bit flip-flop allocation algorithm reduces by 3.55% on average. Also it is shown that the extended noise-aware algorithm is effective in power/ground noise mitigation. In summary, this dissertation presents a new style of multi-bit flip-flop and allocation algorithms, to save clock power consumption and to mitigate power/ground noise.