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Cost-effective Technique for Diagnosing Clock on FPGAs : FPGA 상에서 구현 가능한 경제적인 clock 진단 방법
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- Authors
- Advisor
- 김태환
- Major
- 공과대학 전기·정보공학부
- Issue Date
- 2018-02
- Publisher
- 서울대학교 대학원
- Keywords
- Clock ; Duty cycle ; Frequency ; Measurement ; Delay ; FPGA
- Description
- 학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2018. 2. 김태환.
- Abstract
- A circuit for on-chip measurement of clock frequency and duty cycle for unknown clock is demonstrated. The circuit consists of variable delay, counter and AND gate, and can be implemented on FPGA that has variable delay element without any external supporting circuit and occupies a very small portion of the FPGA. The major benefit over the previous measurement technology is that statistical analysis of the duty cycle of a large number of continuous clock cycles is possible through a single measurement.
- Language
- English
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