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Studies on Resonant Clock Network Synthesis and Design Technology Co-Optimization Framework
공진 클럭 네트워크 합성과 설계 공정 동시 최적화 프레임워크에 관한 연구

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Authors
안세용
Advisor
김태환
Major
공과대학 전기·컴퓨터공학부
Issue Date
2018-08
Publisher
서울대학교 대학원
Description
학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 8. 김태환.
Abstract
In modern VLSI design, there exists a tendency of integrating various com-

ponents including microprocessors, memory blocks, I/O interface and peripher-

als, which can be classified into digital, analog and mixed-signal by their oper-

ation. In general, digital blocks are implemented as synchronous circuits which

operate in sync with the global clock signal and occupy majority portion of

the total chip in terms of area and power consumption. Therefore, saving of

power consumption caused by the clock network is important in achieving a

low-power design. On the other hand, in development of advanced technology

nodes, the sequential product development flow faces a challenge of difficulty in

overall product optimization due to increased TAT (turn-around time) between

design and process development. To resolve this, a DTCO (Design Technology

Co-Optimization) is introduced. Impact of process development to an overall

product can be predicted and analyzed through standard cells which occupy a

majority of digital blocks up to 60%.

First, by introducing on-chip inductors, LC resonance is adopted to reduce

excessive power consumption of clock distribution network. In the presence of

DVFS (Dynamic Voltage/Frequency Scaling), a widely used low power tech-

nique in modern VLSI design, a methodology of synthesizing resonant clock

network is proposed to achieve acceptable power reduction while minimizing

area overhead of inductors and clock driving buffers. Experiments of several

benchmarks show the effectiveness of the proposed method.

Second, a standard cell layout generator is developed to produce cell lay-

outs of which quality is comparable to industrys manually optimized one. The

generator adopts advanced process technology including FinFET transistors,

DP (double patterning) lithography, and complex design rules. In addition, a

DTCO framework which uses the proposed standard cell generator as a core

engine is developed for an effective DTCO work. By experiments using the pro-

posed framework, it is shown that standard cells are generated successfully and

optimization point between design and process can be explored.
Language
English
URI
https://hdl.handle.net/10371/143282
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
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