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블록 캐시와 클록 게이팅을 이용한 H.264/AVC Baseline 디코더의 저전력 설계
The low power design for an H.264/AVC baseline decoder using block caches and clock gating

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Authors
김제선
Advisor
이혁재
Major
전기. 컴퓨터공학부
Issue Date
2011-02
Publisher
서울대학교 대학원
Keywords
H.264 AVC저전력 설계블록 캐시프레임 메모리 압축모듈 수준 클록 게이팅low power designblock cacheframe memory compressionmodule-based clock gating
Description
학위논문 (박사)-- 서울대학교 대학원 : 전기. 컴퓨터공학부, 2011.2. 이혁재.
Language
kor
URI
https://hdl.handle.net/10371/158997

http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000029010
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
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