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College of Engineering/Engineering Practice School (공과대학/대학원)
Dept. of Electrical and Computer Engineering (전기·정보공학부)
Theses (Ph.D. / Sc.D._전기·정보공학부)
(A) study on clock generation circuit using multiphase delay-locked-loop : 다중 위상 지연동기루프를 이용한 클록 발생 회로에 관한 연구
- Authors
- Advisor
- 정덕균
- Major
- 전기·컴퓨터공학부
- Issue Date
- 2011-02
- Publisher
- 서울대학교 대학원
- Keywords
- multiphase DLL ; clock generator ; dual-input interpolating delay ; bang-bang phase detector ; skew calibration
- Description
- 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2011.2. 정덕균.
- Language
- eng
- URI
- https://hdl.handle.net/10371/159084
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000029042
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