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Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

DC Field Value Language
dc.contributor.authorHan, Sang-Il-
dc.contributor.authorBrisolara, Lisane-
dc.contributor.authorCarro, Luigi-
dc.contributor.authorReis, Ricardo-
dc.contributor.authorGuerin, Xavier-
dc.contributor.authorJerraya, Ahmed Amine-
dc.contributor.authorChae, Soo-Ik-
dc.date.accessioned2009-11-26T13:50:32Z-
dc.date.available2009-11-26T13:50:32Z-
dc.date.issued2007-
dc.identifier.citationDesign Automation for Embedded Systems 11(4):249-283en
dc.identifier.issn0929-5585 (print)-
dc.identifier.issn1572-8080 (Online)-
dc.identifier.urihttps://hdl.handle.net/10371/16273-
dc.description.abstractEmerging embedded systems require heterogeneous multiprocessor SoC architectures
that can satisfy both high-performance and programmability. However, as the complexity
of embedded systems increases, software programming on an increasing number
of multiprocessors faces several critical problems, such as multithreaded code generation,
heterogeneous architecture adaptation, short design time, and low cost implementation. In this paper, we present a software code generation flow based on Simulink to address these
problems. We propose a functional modeling style to capture data-intensive and controldependent
target applications, and a system architecture modeling style to seamlessly transform
the functional model into the target architecture. Both models are described using
Simulink. From a system architecture Simulink model, a code generator produces a multithreaded
code, inserting thread and communication primitives to abstract the heterogeneity
of the target architecture. In addition, the multithread code generator called LESCEA applies
the extensions of dataflow based memory optimization techniques, considering both
data and control dependency. Experimental results on aMotion-JPEG decoder and an H.264
decoder show that the proposed multithread code generator enables easy software programming
on different multiprocessor architectures with substantially reduced data memory size
(up to 68.0%) and code memory size (up to 15.9%).
en
dc.language.isoenen
dc.publisherSpringer Verlagen
dc.subjectMultithreaded code generationen
dc.subjectMemory size reductionen
dc.subjectMultiprocessor SoCen
dc.subjectSimulinken
dc.titleMemory-efficient multithreaded code generation from Simulink for heterogeneous MPSoCen
dc.typeArticleen
dc.contributor.AlternativeAuthor한상일-
dc.contributor.AlternativeAuthor채수익-
dc.identifier.doi10.1007/s10617-007-9009-4-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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