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Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yu, Junsu | - |
| dc.contributor.author | Min, Kyung Kyu | - |
| dc.contributor.author | Kim, Yeonwoo | - |
| dc.contributor.author | Kwon, Daewoong | - |
| dc.contributor.author | Park, Byung-Gook | - |
| dc.date.accessioned | 2022-10-19T04:37:55Z | - |
| dc.date.available | 2022-10-19T04:37:55Z | - |
| dc.date.created | 2022-10-04 | - |
| dc.date.issued | 2021-06 | - |
| dc.identifier.citation | 2021 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.29-30 | - |
| dc.identifier.issn | 2161-4636 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/186460 | - |
| dc.description.abstract | To investigate metal-ferroelectric-insulator-semiconductor (MFIS) stack design guidelines for its applications, the ferroelectricity in various IL thicknesses were investigated. As a result, IL has leaky insulator characteristics rather than an ideal dielectric and the MFIS stack shows a critical difference in ferroelectric characteristics. | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE, ELECTRON DEVICES SOC & RELIABILITY GROUP | - |
| dc.title | Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1109/SNW51795.2021.00016 | - |
| dc.citation.journaltitle | 2021 SILICON NANOELECTRONICS WORKSHOP (SNW) | - |
| dc.identifier.wosid | 000712433900015 | - |
| dc.identifier.scopusid | 2-s2.0-85124885500 | - |
| dc.citation.endpage | 30 | - |
| dc.citation.startpage | 29 | - |
| dc.description.isOpenAccess | N | - |
| dc.contributor.affiliatedAuthor | Park, Byung-Gook | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
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