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Core-Shell Dual-Gate Nanowire Synaptic Transistor with Short/Long-Term Plasticity

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dc.contributor.authorAnsari, Md Hasan Raza-
dc.contributor.authorKim, Daehwan-
dc.contributor.authorCho, Seongjae-
dc.contributor.authorLee, Jong-Ho-
dc.contributor.authorPark, Byung-Gook-
dc.date.accessioned2022-10-19T04:37:59Z-
dc.date.available2022-10-19T04:37:59Z-
dc.date.created2022-10-04-
dc.date.issued2021-04-
dc.identifier.citation2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM)-
dc.identifier.urihttps://hdl.handle.net/10371/186465-
dc.description.abstractThis work demonstrates design and performances of core-shell dual-gate nanowire synaptic transistor with short/long term plasticity. The novel structure helps equip better capacitive coupling between dual gates through full depletion of carriers from the Si channel and construct deeper potential well for charge storage, which eventually increases the probability for short-term-to-long-term memory transition by reducing the recombination. The dual-gate operation effectively realizes the short-and the long-term potentiation in the proposed device for hardware-driven neuromorphic system.-
dc.language영어-
dc.publisherIEEE-
dc.titleCore-Shell Dual-Gate Nanowire Synaptic Transistor with Short/Long-Term Plasticity-
dc.typeArticle-
dc.identifier.doi10.1109/EDTM50988.2021.9420876-
dc.citation.journaltitle2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM)-
dc.identifier.wosid000675595800062-
dc.identifier.scopusid2-s2.0-85106483874-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorPark, Byung-Gook-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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