Design and Analysis of Core-Gate Shell-Channel 1T DRAM

Abstract

The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices. CGSC in GAA helps to achieve a fully-depleted channel and form deeper potential well for effective charge storage. The proposed 1T DRAM cell achieves retention time (T-ret) of similar to 3.5 s at 85 degrees C for a gate length of 100 nm and similar to 5 ms at and 125 degrees C with gate length of 10 nm, even at elevated temperatures. The device demonstrates low power (25.18 nW for write "1") and energy (0.02 fJ for read "0") consumptions for DRAM operations.