Publications
Detailed Information
Highly scalable 4F(2) cell transistor for future DRAM technology
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Min, Kyung Kyu | - |
| dc.contributor.author | Hwang, Sungmin | - |
| dc.contributor.author | Lee, Jong-Ho | - |
| dc.contributor.author | Park, Byung-Gook | - |
| dc.date.accessioned | 2022-10-19T04:38:05Z | - |
| dc.date.available | 2022-10-19T04:38:05Z | - |
| dc.date.created | 2022-10-17 | - |
| dc.date.issued | 2020-06 | - |
| dc.identifier.citation | 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), pp.81-82 | - |
| dc.identifier.issn | 2161-4636 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/186473 | - |
| dc.description.abstract | A novel 4F(2) dynamic random access memory (DRAM) cell transistor structure was proposed that can solve various process problems and special failure modes that caused by floating body. The suitability of the transistor scheme for future DRAM technology nodes was also verified. Through this new structure, it can expect to realize 4F(2) DRAM and continuously expand DRAM technology node. | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE | - |
| dc.title | Highly scalable 4F(2) cell transistor for future DRAM technology | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1109/SNW50361.2020.9131608 | - |
| dc.citation.journaltitle | 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) | - |
| dc.identifier.wosid | 000615976200039 | - |
| dc.identifier.scopusid | 2-s2.0-85092207899 | - |
| dc.citation.endpage | 82 | - |
| dc.citation.startpage | 81 | - |
| dc.description.isOpenAccess | N | - |
| dc.contributor.affiliatedAuthor | Park, Byung-Gook | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
- Appears in Collections:
- Files in This Item:
- There are no files associated with this item.
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.