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Influence of Gate to Drain Underlap on Negative Differencial Resistance in Ferroelectric FET

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Authors

Lee, Kitae; Kim, Sihyun; Park, Byung-Gook

Issue Date
2020-06
Publisher
IEEE
Citation
2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), pp.95-96
Abstract
The negative differential resistance in ferroelectric FET was investigated through TCAD device simulation. The gate to drain underlap forms depletion effectively during drain sweep, negative differential resistance is observed remarkably in the large gate to drain underlap.
ISSN
2161-4636
URI
https://hdl.handle.net/10371/186509
DOI
https://doi.org/10.1109/SNW50361.2020.9131415
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