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Study on Etch Slope in Fin and Source/Drain Etch Process of Vertically-Stacked Nanosheet Gate-All-Around MOSFET
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Sihyun | - |
dc.contributor.author | Lee, Kitae | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.date.accessioned | 2022-10-20T00:23:16Z | - |
dc.date.available | 2022-10-20T00:23:16Z | - |
dc.date.created | 2022-10-12 | - |
dc.date.issued | 2020-06 | - |
dc.identifier.citation | 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), pp.99-100 | - |
dc.identifier.issn | 2161-4636 | - |
dc.identifier.uri | https://hdl.handle.net/10371/186510 | - |
dc.description.abstract | The electrical behavior of vertically-stacked nanosheet (NS) gate- all-around MOSFET (GAAFET) having slanted NS channel and source/drain resulted from the etch profile in reactive ion etching processes was investigated through TCAD device simulation. It was observed that the off current (I-OFF) and threshold voltage (V-TH) were variable depending on the etch slope (E/S) and the number of stack (n(stack)). | - |
dc.language | 영어 | - |
dc.publisher | IEEE | - |
dc.title | Study on Etch Slope in Fin and Source/Drain Etch Process of Vertically-Stacked Nanosheet Gate-All-Around MOSFET | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/SNW50361.2020.9131424 | - |
dc.citation.journaltitle | 2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) | - |
dc.identifier.wosid | 000615976200047 | - |
dc.identifier.scopusid | 2-s2.0-85092148201 | - |
dc.citation.endpage | 100 | - |
dc.citation.startpage | 99 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Park, Byung-Gook | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
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