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Local Variation-Aware Transistor Design through Comprehensive Analysis of Various V-dd/Temperatures Using Sub-7nm Advanced FinFET Technology
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Soyoun | - |
dc.contributor.author | Kim, Seung Kwon | - |
dc.contributor.author | Yamaguchi, Taiko | - |
dc.contributor.author | Kim, Jae Chul | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.contributor.author | Yasuda-Masuoka, Yuri | - |
dc.contributor.author | Kwon, S. D. | - |
dc.date.accessioned | 2022-10-20T00:23:17Z | - |
dc.date.available | 2022-10-20T00:23:17Z | - |
dc.date.created | 2022-10-12 | - |
dc.date.issued | 2020-06 | - |
dc.identifier.citation | 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, p. 9265089 | - |
dc.identifier.issn | 0743-1562 | - |
dc.identifier.uri | https://hdl.handle.net/10371/186511 | - |
dc.description.abstract | In this paper, key contributors to local variability of sub-7nm FinFET has been identified in various operating environments. Through a comprehensive analysis, different root-cause for high and low temperature region have been revealed and confirmed by advanced Si wafer for the first time. Moreover, a local variation-aware transistor was successfully demonstrated to reduce sigma V-min distribution by 0.5x and 0.3x at cold temperature. | - |
dc.language | 영어 | - |
dc.publisher | IEEE | - |
dc.title | Local Variation-Aware Transistor Design through Comprehensive Analysis of Various V-dd/Temperatures Using Sub-7nm Advanced FinFET Technology | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/VLSITechnology18217.2020.9265089 | - |
dc.citation.journaltitle | 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | - |
dc.identifier.wosid | 000668063000073 | - |
dc.identifier.scopusid | 2-s2.0-85098111278 | - |
dc.citation.startpage | 9265089 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Park, Byung-Gook | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
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