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Local Variation-Aware Transistor Design through Comprehensive Analysis of Various V-dd/Temperatures Using Sub-7nm Advanced FinFET Technology

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dc.contributor.authorKim, Soyoun-
dc.contributor.authorKim, Seung Kwon-
dc.contributor.authorYamaguchi, Taiko-
dc.contributor.authorKim, Jae Chul-
dc.contributor.authorPark, Byung-Gook-
dc.contributor.authorYasuda-Masuoka, Yuri-
dc.contributor.authorKwon, S. D.-
dc.date.accessioned2022-10-20T00:23:17Z-
dc.date.available2022-10-20T00:23:17Z-
dc.date.created2022-10-12-
dc.date.issued2020-06-
dc.identifier.citation2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, p. 9265089-
dc.identifier.issn0743-1562-
dc.identifier.urihttps://hdl.handle.net/10371/186511-
dc.description.abstractIn this paper, key contributors to local variability of sub-7nm FinFET has been identified in various operating environments. Through a comprehensive analysis, different root-cause for high and low temperature region have been revealed and confirmed by advanced Si wafer for the first time. Moreover, a local variation-aware transistor was successfully demonstrated to reduce sigma V-min distribution by 0.5x and 0.3x at cold temperature.-
dc.language영어-
dc.publisherIEEE-
dc.titleLocal Variation-Aware Transistor Design through Comprehensive Analysis of Various V-dd/Temperatures Using Sub-7nm Advanced FinFET Technology-
dc.typeArticle-
dc.identifier.doi10.1109/VLSITechnology18217.2020.9265089-
dc.citation.journaltitle2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY-
dc.identifier.wosid000668063000073-
dc.identifier.scopusid2-s2.0-85098111278-
dc.citation.startpage9265089-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorPark, Byung-Gook-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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