Ge Condensation Process for High ON/OFF Ratio of SiGe Gate-All-Around Nanowire Tunnel Field-Effect Transistor

Abstract

In this study, we suggest an improvement method for high ON/OFF ratio and steep subthreshold swing (SS) which are suitable for gate-all-around (GAA) SiGe tunnel field-effect Transistor (TFET). Through technology-computer-aided-design (TCAD) simulation, the effect of Ge condensation on the device performance is examined. Furthermore, SiGe nanowire (NW) channel with high Ge ratio (over 70%) is successfully formed and the advantage of gradually-distributed Ge throughout the SiGe NW is also investigated.