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Modeling of Lateral Migration Mechanism of Holes in 3D NAND Flash Memory Charge Trap Layer during Retention Operation
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, Jaeyeol | - |
| dc.contributor.author | Shin, Hyungcheol | - |
| dc.date.accessioned | 2022-10-26T07:21:02Z | - |
| dc.date.available | 2022-10-26T07:21:02Z | - |
| dc.date.created | 2022-10-20 | - |
| dc.date.issued | 2019-06 | - |
| dc.identifier.citation | 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.61-62 | - |
| dc.identifier.issn | 2161-4636 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/186746 | - |
| dc.description.abstract | In this paper, we analyzed lateral migration mechanism of holes (LM) in 3D NAND Flash memory during retention operation. Retention characteristics were investigated using Technology Computer-Aided Design (TCAD) simulation and modeled using Weibull cumulative distribution function (WCD). Time-constant (tau) at various temperatures were extracted through the modeled equation. Finally, the activation energy (E-a) of LM was extracted by applying to the Arrhenius equation. | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE | - |
| dc.title | Modeling of Lateral Migration Mechanism of Holes in 3D NAND Flash Memory Charge Trap Layer during Retention Operation | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.23919/SNW.2019.8782975 | - |
| dc.citation.journaltitle | 2019 SILICON NANOELECTRONICS WORKSHOP (SNW) | - |
| dc.identifier.wosid | 000501001400029 | - |
| dc.identifier.scopusid | 2-s2.0-85070916661 | - |
| dc.citation.endpage | 62 | - |
| dc.citation.startpage | 61 | - |
| dc.description.isOpenAccess | N | - |
| dc.contributor.affiliatedAuthor | Shin, Hyungcheol | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
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