Publications

Detailed Information

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS

DC Field Value Language
dc.contributor.authorPark, Kwanseo-
dc.contributor.authorLee, Kwangho-
dc.contributor.authorCho, Sung-Yong-
dc.contributor.authorLee, Jinhyung-
dc.contributor.authorHwang, Jeongho-
dc.contributor.authorChoo, Min-Seong-
dc.contributor.authorJeong, Deog-Kyoon-
dc.date.accessioned2022-10-26T07:21:05Z-
dc.date.available2022-10-26T07:21:05Z-
dc.date.created2022-10-20-
dc.date.issued2019-06-
dc.identifier.citation2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C194-C195-
dc.identifier.urihttps://hdl.handle.net/10371/186750-
dc.description.abstractThis paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme, The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is 25 mu s with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm(2)-
dc.language영어-
dc.publisherIEEE-
dc.titleA 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS-
dc.typeArticle-
dc.identifier.doi10.23919/VLSIC.2019.8778157-
dc.citation.journaltitle2019 SYMPOSIUM ON VLSI CIRCUITS-
dc.identifier.wosid000531736500066-
dc.identifier.scopusid2-s2.0-85073894393-
dc.citation.endpageC195-
dc.citation.startpageC194-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorJeong, Deog-Kyoon-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
Appears in Collections:
Files in This Item:
There are no files associated with this item.

Altmetrics

Item View & Download Count

  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Share