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A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Kwanseo | - |
dc.contributor.author | Lee, Kwangho | - |
dc.contributor.author | Cho, Sung-Yong | - |
dc.contributor.author | Lee, Jinhyung | - |
dc.contributor.author | Hwang, Jeongho | - |
dc.contributor.author | Choo, Min-Seong | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2022-10-26T07:21:05Z | - |
dc.date.available | 2022-10-26T07:21:05Z | - |
dc.date.created | 2022-10-20 | - |
dc.date.issued | 2019-06 | - |
dc.identifier.citation | 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C194-C195 | - |
dc.identifier.uri | https://hdl.handle.net/10371/186750 | - |
dc.description.abstract | This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme, The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is 25 mu s with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm(2) | - |
dc.language | 영어 | - |
dc.publisher | IEEE | - |
dc.title | A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS | - |
dc.type | Article | - |
dc.identifier.doi | 10.23919/VLSIC.2019.8778157 | - |
dc.citation.journaltitle | 2019 SYMPOSIUM ON VLSI CIRCUITS | - |
dc.identifier.wosid | 000531736500066 | - |
dc.identifier.scopusid | 2-s2.0-85073894393 | - |
dc.citation.endpage | C195 | - |
dc.citation.startpage | C194 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Jeong, Deog-Kyoon | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
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