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A 0.1 1.62-to-10.8Gb/s Video interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Jinhyung | - |
dc.contributor.author | Lee, Kwangho | - |
dc.contributor.author | Kim, Hyojun | - |
dc.contributor.author | Kim, Byungmin | - |
dc.contributor.author | Park, Kwanseo | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2022-10-26T07:21:06Z | - |
dc.date.available | 2022-10-26T07:21:06Z | - |
dc.date.created | 2022-10-20 | - |
dc.date.issued | 2019-06 | - |
dc.identifier.citation | 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C198-C199 | - |
dc.identifier.uri | https://hdl.handle.net/10371/186751 | - |
dc.description.abstract | This paper presents a 65nm CMOS 1.624o -10.8(112/s video interface receiver with fully adaptive equalizers incorporating CTLE and 2 -tap DEE, Sign-sign least -mean-squares (SSLMS) algorithm is used for not only the DFE but also the CTLE adaptation to reduce power consumption and extra hardware. An un-even data level is proposed for the optimum locking of the adaptation in the presence of a pre cursor. The receiver achieves BER of 10-12 at 34dB loss channel, occupies 0.174mm2, and consumes 37.2mW at 10.8Gb/s. | - |
dc.language | 영어 | - |
dc.publisher | IEEE | - |
dc.title | A 0.1 1.62-to-10.8Gb/s Video interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level | - |
dc.type | Article | - |
dc.citation.journaltitle | 2019 SYMPOSIUM ON VLSI CIRCUITS | - |
dc.identifier.wosid | 000531736500068 | - |
dc.citation.endpage | C199 | - |
dc.citation.startpage | C198 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Jeong, Deog-Kyoon | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
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