A 370-fJ/b, 0.0056 mm(2)/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop

Abstract

This paper presents a data (DQ) receiver for HBM3 with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift. The self-tracking loop achieves low power and small area by utilizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage difference and detects the phase skew from the voltage difference, An offset calibration scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing circuits by taking advantage of the write training of HBM, Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4,8 Gb/s and occupies 0.0056 mm(2). The experimental results show that the DQ receiver operates without any performance degradation under a 10% supply variation.