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Influence of Etch Profiles on the Leakage Current and Capacitance of 3-D DRAM Storage Capacitors

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dc.contributor.authorShin, Seongun-
dc.contributor.authorYoon, Gyuhan-
dc.contributor.authorChoi, Woo Young-
dc.date.accessioned2022-10-26T07:21:10Z-
dc.date.available2022-10-26T07:21:10Z-
dc.date.created2022-10-20-
dc.date.issued2019-04-
dc.identifier.citationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.19 No.2, pp.208-213-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://hdl.handle.net/10371/186757-
dc.description.abstractThe influence of etch profiles on leakage current and capacitance of three-dimensional (3-D) dynamic random access memory (DRAM) storage capacitors is investigated by using full 3-D technology computer-aided design (TCAD) simulation. According to the simulation results calibrated by experimental data, as the ratio of bottom critical dimension (CDBOT) to top critical dimension (CDTOP) of a DRAM storage capacitor decreases, storage capacitance (C-s) decreases while leakage current (I-leak) increases. Thus, it is important to achieve steep etch profiles during the fabrication of DRAM storage capacitors for higher DRAM capacity and longer refresh time.-
dc.language영어-
dc.publisher대한전자공학회-
dc.titleInfluence of Etch Profiles on the Leakage Current and Capacitance of 3-D DRAM Storage Capacitors-
dc.typeArticle-
dc.identifier.doi10.5573/JSTS.2019.19.2.208-
dc.citation.journaltitleJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.identifier.wosid000465573000011-
dc.identifier.scopusid2-s2.0-85067062758-
dc.citation.endpage213-
dc.citation.number2-
dc.citation.startpage208-
dc.citation.volume19-
dc.identifier.kciidART002459022-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Young-
dc.type.docTypeArticle-
dc.description.journalClass1-
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