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On-current Modeling of 70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions

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dc.contributor.authorChoi, Woo Young-
dc.contributor.authorLim, In Eui-
dc.contributor.authorJhon, Heesauk-
dc.contributor.authorYoon, Gyuhan-
dc.date.accessioned2022-10-26T07:21:17Z-
dc.date.available2022-10-26T07:21:17Z-
dc.date.created2022-10-20-
dc.date.issued2018-04-
dc.identifier.citationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.18 No.2, pp.131-138-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://hdl.handle.net/10371/186767-
dc.description.abstractBased on the drain-avalanche-hot-carrier (DAHC-) mechanism, a stress-bias-dependent on-current model is proposed for 70-nm p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) by using only one device parameter: channel length variation (Delta L-ch). The proposed model describes the influence of drain and gate stress bias on the on-current of PMOSFETs successfully. It is a simple and effective method of predicting the on-current variation for more reliable circuit operation.-
dc.language영어-
dc.publisher대한전자공학회-
dc.titleOn-current Modeling of 70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions-
dc.typeArticle-
dc.identifier.doi10.5573/JSTS.2018.18.2.131-
dc.citation.journaltitleJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.identifier.wosid000432340100002-
dc.identifier.scopusid2-s2.0-85046414656-
dc.citation.endpage138-
dc.citation.number2-
dc.citation.startpage131-
dc.citation.volume18-
dc.identifier.kciidART002338816-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Young-
dc.type.docTypeArticle; Proceedings Paper-
dc.description.journalClass1-
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