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Monolithic three-dimensional tunnel FET-nanoelectromechanical hybrid reconfigurable logic circuits

DC Field Value Language
dc.contributor.authorKim, Seung Kyu-
dc.contributor.authorChoi, Woo Young-
dc.date.accessioned2022-10-26T07:21:23Z-
dc.date.available2022-10-26T07:21:23Z-
dc.date.created2022-10-20-
dc.date.issued2017-03-
dc.identifier.citationJapanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD12-
dc.identifier.issn0021-4922-
dc.identifier.urihttps://hdl.handle.net/10371/186775-
dc.description.abstractMonolithic three-dimensional (M3D) reconfigurable logic (RL) circuits of tunnel field-effect transistors (TFETs)-nanoelectromechanical (NEM) memory switches have been proposed, simulated and demonstrated in order to overcome the limitations of CMOS-only RL circuits. A TFET is considered as one of the most promising extremely-low-power logic devices thanks to its abrupt on-off transition as well as low off-current (I-off) and a NEM memory switch is a good solution to signal path routing thanks to its nonvolatile storage of data signal paths and stable rail-to-rail voltage swing. In our proposed RL circuits, NEM memory switch routing parts are integrated over complementary TFET logic circuits by using conventional CMOS backend process. (C) 2017 The Japan Society of Applied Physics-
dc.language영어-
dc.publisherIOP Publishing Ltd-
dc.titleMonolithic three-dimensional tunnel FET-nanoelectromechanical hybrid reconfigurable logic circuits-
dc.typeArticle-
dc.identifier.doi10.7567/JJAP.56.04CD12-
dc.citation.journaltitleJapanese Journal of Applied Physics-
dc.identifier.wosid000414623100017-
dc.identifier.scopusid2-s2.0-85017101423-
dc.citation.number4S-
dc.citation.startpage04CD12-
dc.citation.volume56-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Young-
dc.type.docTypeArticle-
dc.description.journalClass1-
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