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Influence of Intercell Trapped Charge on Vertical NAND Flash Memory

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dc.contributor.authorChoi, Woo Young-
dc.contributor.authorKwon, Hyug Su-
dc.contributor.authorKim, Yong Jun-
dc.contributor.authorLee, Byungin-
dc.contributor.authorYoo, Hyunseung-
dc.contributor.authorChoi, Sangmoo-
dc.contributor.authorCho, Gyu-Seog-
dc.contributor.authorPark, Sung-Kye-
dc.date.accessioned2022-10-26T07:21:24Z-
dc.date.available2022-10-26T07:21:24Z-
dc.date.created2022-10-20-
dc.date.issued2017-02-
dc.identifier.citationIEEE Electron Device Letters, Vol.38 No.2, pp.164-167-
dc.identifier.issn0741-3106-
dc.identifier.urihttps://hdl.handle.net/10371/186776-
dc.description.abstractThe influence of intercell trapped charge (ITC)-the charge trapped at the inter-cell nitride regions by fringe electric fields during programand erase operations-on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degradation mechanisms such as tunnel oxide damage, ITC deteriorates the transconductance and read current of VNAND flash memory cells. The influence of ITC-induced degradationon VNAND flashmemory is discussed, using both simulation and experimental results. A solution for ITC suppression is also proposed: the use of low-k intercell regions.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleInfluence of Intercell Trapped Charge on Vertical NAND Flash Memory-
dc.typeArticle-
dc.identifier.doi10.1109/LED.2016.2643278-
dc.citation.journaltitleIEEE Electron Device Letters-
dc.identifier.wosid000395470700003-
dc.identifier.scopusid2-s2.0-85011277348-
dc.citation.endpage167-
dc.citation.number2-
dc.citation.startpage164-
dc.citation.volume38-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Young-
dc.type.docTypeArticle-
dc.description.journalClass1-
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