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Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot- carrier Stress Bias Conditions
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- Authors
- Issue Date
- 2017-02
- Publisher
- 대한전자공학회
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.17 No.1, pp.94-100
- Abstract
- Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (triangle L-ch) and threshold voltage shift (triangle V-th). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.
- ISSN
- 1598-1657
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