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Influence of line-edge roughness on multiple-gate tunnel field-effect transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Woo Young | - |
dc.date.accessioned | 2022-10-26T07:21:25Z | - |
dc.date.available | 2022-10-26T07:21:25Z | - |
dc.date.created | 2022-10-20 | - |
dc.date.issued | 2017-02 | - |
dc.identifier.citation | Japanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD06 | - |
dc.identifier.issn | 0021-4922 | - |
dc.identifier.uri | https://hdl.handle.net/10371/186778 | - |
dc.description.abstract | The influence of fin-line-edge roughness (fin-LER) and gate-LER on multiple-gate (MG) tunnel field-effect transistors (TFETs) has been investigated compared with MG MOSFETs by using full three-dimensional technology computer-aided design (TCAD) simulation. From simulation results, two interesting results have been observed. First, MG TFETs show much less severe gate-LER than MG MOSFETs, which means that only fin-LER can be considered when evaluating the total LER of MG TFETs. Second, TFETs show similar to 3x more LER improvement than MOSFETs when their structures are changed from double-gate (DG) to triple-gate (TG) ones. Our findings provide the useful design guidelines of variation-tolerant TFETs. (C) 2017 The Japan Society of Applied Physics | - |
dc.language | 영어 | - |
dc.publisher | IOP Publishing Ltd | - |
dc.title | Influence of line-edge roughness on multiple-gate tunnel field-effect transistors | - |
dc.type | Article | - |
dc.identifier.doi | 10.7567/JJAP.56.04CD06 | - |
dc.citation.journaltitle | Japanese Journal of Applied Physics | - |
dc.identifier.wosid | 000414623100012 | - |
dc.identifier.scopusid | 2-s2.0-85017133756 | - |
dc.citation.number | 4S | - |
dc.citation.startpage | 04CD06 | - |
dc.citation.volume | 56 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Woo Young | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
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