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Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

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dc.contributor.authorChoi, Woo Young-
dc.date.accessioned2022-10-26T07:21:27Z-
dc.date.available2022-10-26T07:21:27Z-
dc.date.created2022-10-20-
dc.date.issued2017-01-
dc.identifier.citationJapanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD01-
dc.identifier.issn0021-4922-
dc.identifier.urihttps://hdl.handle.net/10371/186780-
dc.description.abstractThe effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal-oxide-semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V-th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs. (C) 2017 The Japan Society of Applied Physics-
dc.language영어-
dc.publisherIOP Publishing Ltd-
dc.titleEffects of drain bias on the statistical variation of double-gate tunnel field-effect transistors-
dc.typeArticle-
dc.identifier.doi10.7567/JJAP.56.04CD01-
dc.citation.journaltitleJapanese Journal of Applied Physics-
dc.identifier.wosid000414623100009-
dc.identifier.scopusid2-s2.0-85017095517-
dc.citation.number4S-
dc.citation.startpage04CD01-
dc.citation.volume56-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Young-
dc.type.docTypeArticle-
dc.description.journalClass1-
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