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Design guidelines of tunnelling field-effect transistors for the suppression of work-function variation
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, W. Y. | - |
| dc.date.accessioned | 2022-10-26T07:21:35Z | - |
| dc.date.available | 2022-10-26T07:21:35Z | - |
| dc.date.created | 2022-10-20 | - |
| dc.date.issued | 2015-10 | - |
| dc.identifier.citation | Electronics Letters, Vol.51 No.22, pp.1819-1820 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/186792 | - |
| dc.description.abstract | Design guidelines to suppress the work-function variation (WFV) effects of tunnelling field-effect transistors (TFETs) have been discussed in comparison with metal-oxide-semiconductor FETs for the first time. The effects of metal-gate materials and their grain size on the WFV have been investigated. The simulation results show that the selection of appropriate gate material and the reduction of metal grain size are the effective solutions to the WFV of TFETs. | - |
| dc.language | 영어 | - |
| dc.publisher | Institute of Electrical Engineers | - |
| dc.title | Design guidelines of tunnelling field-effect transistors for the suppression of work-function variation | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1049/el.2015.2625 | - |
| dc.citation.journaltitle | Electronics Letters | - |
| dc.identifier.wosid | 000364202500052 | - |
| dc.identifier.scopusid | 2-s2.0-84946047542 | - |
| dc.citation.endpage | 1820 | - |
| dc.citation.number | 22 | - |
| dc.citation.startpage | 1819 | - |
| dc.citation.volume | 51 | - |
| dc.description.isOpenAccess | N | - |
| dc.contributor.affiliatedAuthor | Choi, W. Y. | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
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