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Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

DC Field Value Language
dc.contributor.authorLee, Min Jin-
dc.contributor.authorChoi, Woo Young-
dc.date.accessioned2022-10-26T07:21:48Z-
dc.date.available2022-10-26T07:21:48Z-
dc.date.created2022-10-20-
dc.date.issued2012-10-
dc.identifier.citationIEEE Electron Device Letters, Vol.33 No.10, pp.1459-1461-
dc.identifier.issn0741-3106-
dc.identifier.urihttps://hdl.handle.net/10371/186811-
dc.description.abstractThis letter discusses the effects of device geometry, such as channel layer thickness and multiple-gate structure on hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). According to simulation results, contrary to conventional TFETs or MOSFETs, HG TFETs show improved subthreshold swing (SS) for increasing channel thickness or decreasing number of gates. The trend with ON-current I-ON depends on operating voltage V-DD.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleEffects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors-
dc.typeArticle-
dc.identifier.doi10.1109/LED.2012.2206790-
dc.citation.journaltitleIEEE Electron Device Letters-
dc.identifier.wosid000309364600042-
dc.identifier.scopusid2-s2.0-84866924046-
dc.citation.endpage1461-
dc.citation.number10-
dc.citation.startpage1459-
dc.citation.volume33-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Young-
dc.type.docTypeArticle-
dc.description.journalClass1-
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