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Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Min Jin | - |
dc.contributor.author | Choi, Woo Young | - |
dc.date.accessioned | 2022-10-26T07:21:48Z | - |
dc.date.available | 2022-10-26T07:21:48Z | - |
dc.date.created | 2022-10-20 | - |
dc.date.issued | 2012-10 | - |
dc.identifier.citation | IEEE Electron Device Letters, Vol.33 No.10, pp.1459-1461 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://hdl.handle.net/10371/186811 | - |
dc.description.abstract | This letter discusses the effects of device geometry, such as channel layer thickness and multiple-gate structure on hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). According to simulation results, contrary to conventional TFETs or MOSFETs, HG TFETs show improved subthreshold swing (SS) for increasing channel thickness or decreasing number of gates. The trend with ON-current I-ON depends on operating voltage V-DD. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LED.2012.2206790 | - |
dc.citation.journaltitle | IEEE Electron Device Letters | - |
dc.identifier.wosid | 000309364600042 | - |
dc.identifier.scopusid | 2-s2.0-84866924046 | - |
dc.citation.endpage | 1461 | - |
dc.citation.number | 10 | - |
dc.citation.startpage | 1459 | - |
dc.citation.volume | 33 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Woo Young | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
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