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Nanoelectromechanical (NEM) Devices for Logic and Memory Applications

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dc.contributor.authorKwon, Hyug Su-
dc.contributor.authorChoi, Woo Young-
dc.date.accessioned2022-10-26T07:21:51Z-
dc.date.available2022-10-26T07:21:51Z-
dc.date.created2022-07-18-
dc.date.issued2022-06-
dc.identifier.citationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.22 No.3, pp.188-197-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://hdl.handle.net/10371/186815-
dc.description.abstract© 2022, Institute of Electronics Engineers of Korea. All rights reserved.—Recent research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.-
dc.language영어-
dc.publisher대한전자공학회-
dc.titleNanoelectromechanical (NEM) Devices for Logic and Memory Applications-
dc.typeArticle-
dc.identifier.doi10.5573/JSTS.2022.22.3.188-
dc.citation.journaltitleJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.identifier.wosid000831668000008-
dc.identifier.scopusid2-s2.0-85133553690-
dc.citation.endpage197-
dc.citation.number3-
dc.citation.startpage188-
dc.citation.volume22-
dc.identifier.kciidART002848519-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Young-
dc.type.docTypeArticle-
dc.description.journalClass1-
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