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A 64 Gb/s 1.5 pJ/bit PAM-4 Transmitter with 3-Tap FFE and G(m)-Regulated Active-Feedback Driver in 28 nm CMOS
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ju, Haram | - |
dc.contributor.author | Choi, Moon-Chul | - |
dc.contributor.author | Jeong, Gyu-Seob | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2022-10-26T07:22:19Z | - |
dc.date.available | 2022-10-26T07:22:19Z | - |
dc.date.created | 2022-10-21 | - |
dc.date.issued | 2018-06 | - |
dc.identifier.citation | 2018 IEEE SYMPOSIUM ON VLSI CIRCUITS, pp.51-52 | - |
dc.identifier.uri | https://hdl.handle.net/10371/186855 | - |
dc.description.abstract | This paper presents a low-power implementation of a 64 Gb/s PAM-4 transmitter (TX) by using 3-tap feed-forward equalization (FFE) and G(m) -regulated active-feedback driver. The FFE tap generation is merged into serializer to minimize the overhead of FFE, by replacing a power-hungry delay generator. An active-feedback inverter based driver is also proposed to achieve a larger output swing compared with a resistive-feedback driver with limited output swing. The prototype chip is fabricated in 28nm CMOS technology and occupies 0.185 mm(2). The proposed TX achieves the data rate of 64 Gb/s while consuming 97.2 mW, which exhibits the state-of-the-art energy efficiency of 1.5 pJ/b. | - |
dc.language | 영어 | - |
dc.publisher | IEEE | - |
dc.title | A 64 Gb/s 1.5 pJ/bit PAM-4 Transmitter with 3-Tap FFE and G(m)-Regulated Active-Feedback Driver in 28 nm CMOS | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/VLSIC.2018.8502380 | - |
dc.citation.journaltitle | 2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | - |
dc.identifier.wosid | 000853983300019 | - |
dc.identifier.scopusid | 2-s2.0-85056849408 | - |
dc.citation.endpage | 52 | - |
dc.citation.startpage | 51 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Jeong, Deog-Kyoon | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
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