Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits

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Lee, Kyu-Ho; Kwon, Dongseok; Woo, Sung Yun; Ko, Jong Hyun; Choi, Woo Young; Park, Byung-Gook; Lee, Jong-Ho

Issue Date
Institute of Electrical and Electronics Engineers
IEEE Transactions on Electron Devices
In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array (25 x 4 synapses) and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). We investigate the synaptic behavior of the CTF cells and the operating principle of the neuron circuits. Under the given operating conditions, the fabricated SPB consistently exhibits a highly linear relationship (R-2 > 0.999) between the current sum and the output spike frequency, enabling the SNNs to precisely mimic the layer of artificial neural networks (ANNs) with rectified linear unit (ReLU) activation function. Based on the fabricated SPB, a single-layer SNN is experimentally demonstrated for classifying the 5 x 5 digit patterns.
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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