Sub-10 nm Advanced FinFET Design for Different Applications in Various Vdd and Temperature Operation Ranges

Abstract

An advanced FinFET design is identified to improve both variation and minimum operation voltage (V-min) in various temperature and supply voltage (V-dd) ranges, using sub-10 nm FinFET transistors. Through a clarification of each electrical parameter's impact on both variation and operation voltage, a suitable FinFET design is successfully demonstrated to reduce I-eff variation by 0.4x, as well as Idoff variation by 0.8x in various V-dd ranges. This paper also provides Tr. design to improve V-min by 35 mV with the switching energy 0.87x reduction.