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Elimination of the gate and drain bias stresses in I-V characteristics of WSe2 FETs by using dual channel pulse measurement

Cited 12 time in Web of Science Cited 11 time in Scopus
Authors

Park, Jun-Mo; Cho, In-Tak; Kang, Won-Mook; Park, Byung-Gook; Lee, Jong-Ho

Issue Date
2016-08
Publisher
American Institute of Physics
Citation
Applied Physics Letters, Vol.109 No.5, p. 053503
Abstract
Intrinsic transfer and output characteristics of WSe2 field effect transistors are obtained by adopting the dual channel pulsed I-V measurement. Due to the DC gate bias stress during the measurement, a large hysteresis is observed and increased with increasing the sweeping range of the gate bias in the transfer curves. In addition, as a drain bias increases, the drain bias stress during the measurement induces the threshold voltage shift. The output curves measured by a DC method are significantly affected by the drain bias sweeping direction and the previous measurement, which leads to a large error in the analysis. By using the dual channel pulsed I-V measurement with a short turn-on time (10(-4) s), a long turn-off time (1 s), and a base voltage (gate and drain bias during turn-off time) of 0V, hysteretic behaviors caused by the gate bias stress and threshold voltage shift due to the drain bias stress in transfer curves are eliminated. The effect of the drain bias sweeping direction and the previous measurement in output curves are also eliminated, and the output curves show a typical field effect behavior. The intrinsic characteristics of WSe2 field effect transistors show negligible hysteresis and remarkably enhanced mobility (similar to 200 cm(2)/Vs), and higher current drive capability compared to those of DC measurements. Published by AIP Publishing.
ISSN
0003-6951
URI
https://hdl.handle.net/10371/195405
DOI
https://doi.org/10.1063/1.4960459
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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