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A Next-Generation Cryogenic Processor Architecture

Cited 7 time in Web of Science Cited 8 time in Scopus
Authors

Byun, Ilkwon; Min, Dongmoon; Lee, Gyuhyeon; Na, Seongmin; Kim, Jangwoo

Issue Date
2021-05
Publisher
Institute of Electrical and Electronics Engineers
Citation
IEEE Micro, Vol.41 No.3, pp.80-86
Abstract
Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device's leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture even with its high potentials in performance, power, and area efficiency. In this article, we first develop CryoCore-Model, a cryogenic processor modeling framework that can accurately estimate the maximum clock frequency of processor models running at 77 K. Next, driven by the modeling tool, we design CryoCore, a 77 K-optimal core microarchitecture to maximize the core's performance and area efficiency while minimizing the cooling cost. The proposed cryogenic processor architecture, in this article, achieves the large performance improvement and power reduction and, thus, contributes to the future of high-performance and power-efficient computer systems.
ISSN
0272-1732
URI
https://hdl.handle.net/10371/195626
DOI
https://doi.org/10.1109/MM.2021.3070133
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