10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique

Abstract

Sampling PLLs (SPLLs) are currently the most popular architecture for generating ultralow-jitter signals due to their high-gain sampling phase detectors (SPDs) that can significantly reduce in-band phase noise (PN). However, to maintain this advantage even in the fractional-N mode, SPLLs must remove the quantization error (Q-error) of the ΔΣM very precisely. The use of a digital-to-time converter (DTC) before the SPD [1] (top left of Fig. 10.5.1) is a common solution, but the inherent non-linearity (NL) of the DTC, i.e., NLDTC, introduces fractional spurs and the leakage of the Q-error, which increases the inband PN. There are two approaches that are used widely to reduce NLDTC. The first approach (1) is to use a typical DTC and then compensate for NLDTC using a digital predistortion (DPD) that modifies the accumulated ΔΣM code, i.e., DAQ, to have the inverse function of NLDTC [2]. However, this technique requires significant design resources (in terms of power and area) to achieve high accuracy. The second approach (2) is to design a linear DTC with an inherently small NLDTC. The constant-slope DTCs (CS-DTCs) reduced NLDTC by charging a capacitor with the same ramp rate regardless of the initial voltage determined by DAQ. The inverse constant-slope DTC (ICS-DTC) [3] further reduced NLDTC by generating the initial voltage by controlling the precharging time as a multiple of the VCO period (TVCO), i.e., k·TVCO (k is an integer), to remove the voltage dependence of the capacitor and the current. However, the downside is that a longer precharge time (or k·TVCO) is required to achieve the higher DTC resolution, which increases the thermal noise of the DTC and hence the in-band PN.