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4.6 A 47fs-rms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth

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Authors

Bang, Jooeun; Kim, Jaeho; Jung, Seohee; Park, Suneui; Choi, Jaehyouk

Issue Date
2023
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2023-February, pp.84-86
Abstract
The W and D bands located at the lower boundary of the sub-THz spectrum are considered viable candidates for CMOS-based wireless-communication systems to utilize sub-THz frequencies. However, there are still many challenges to overcome before these bands can be put to practical use. One of the most critical challenges is the design of a frequency synthesizer to generate sub-THz local-oscillator (LO) signals with extremely low jitter. This is because the value of the rms jitter required to support the target EVM decreases as the LO frequency increases, e.g., the rms jitter of an LO signal at 100GHz must be reduced to less than 50fs to satisfy -30dB EVM for 64-QAM. To achieve such low rms jitter, the bandwidth of a PLL must be extended to suppress the poor phase noise (PN) of a sub-THz VCO, but it cannot sufficiently filter the high in-band PN that is amplified by a large multiplication factor (M). Thus, to date, cascaded PLLs with frequency multipliers (FMs) [1], [2] have been used extensively since they can solve this dilemma. However, their multi-stage architectures require large power and silicon area. As a single-stage solution, sub-sampling PLLs (SSPLLs) are more efficient in terms of power and area. Since the high phase-error (PhimathsfERR)-detection gain (KmathsfPD) of the sub-sampling PD (SSPD) can reduce the in-band PN dramatically, SSPLLs can have an extended bandwidth. However, the problem is that this merit of SSPLLs is no longer valid when the frequency of the VCO, fmathsfVCO, is increased much higher than the frequency of the output pole of the SSPD, fmathsfRC. The top of Fig. 4.6.1 shows this situation, in which the value of KmathsfPD is reduced significantly as the PhimathsfERR is suppressed by the pole of the SSPD. Recently, the power-gating injection-locked-FM PD (PG-ILFM PD) was presented to address this KmathsfPD-reduction problem of the SSPD at sub-THz frequencies [3]. First, it generates a discontinuous but ultra-low-jitter signal, SmathsfILFM, at the exact target frequency, Mcdot ftextREF, using a replica VCO (R-VCO). Then, by mixing this StextILFM with the output of the main VCO (M-VCO), SmathsfVCO, the PG-ILFM PD downconverts the PhimathsfERR information in SmathsfVC0 to the baseband before it is suppressed by the output pole of the PD. Thus, it can maintain a high KmathsfPD and low in-band PN even when fmathsfVCO exceeds 100GHz.
ISSN
0193-6530
URI
https://hdl.handle.net/10371/199369
DOI
https://doi.org/10.1109/ISSCC42615.2023.10067293
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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