A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique

Abstract

This work presents a low-jitter and high-frequency ring-oscillator (RO)-based multiplying DLL (MDLL). To overcome the limit of conventional MDLLs that use a series MUX for edge switching, the proposed MDLL uses a power-gating (PG) technique to periodically remove the accumulated jitter of the RO. So, it can achieve a very low jitter even at a very high output frequency above 10GHz with a large multiplication factor (N) over 100. The proposed hybrid accumulator (HACC) allows the calibrator to achieve high resolution and wide bandwidth concurrently. The measured rms jitter and reference spur at 12.24GHz (N =102) were 122fs and -60 dBc, respectively.