A Low-Jitter Ring-DCO-Based Fractional-<i>N</i> Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

Abstract

This work presents a fractional-N ring-oscillator (RO)-based digital phase-locked loop (DPLL). To achieve ultralow jitter, the proposed RO-DPLL used a technique to reduce the dominant source of in-band noise, i.e., the thermal noise of the digital-to-time converters (DTCs). A key building block of this technique is the quadruple-timing-margin phase selector (QTM-PS) that dynamically selects the proper phase among the eight phases of the RO, effectively reducing the required dynamic range of the DTCs and, thus, suppressing the thermal noise significantly. Based on the reduced in-band noise, the dual-edge generator (DEG) doubles the bandwidth of the DPLL, further suppressing the jitter of the RO. The integrated background calibrator (IBC) that can perform multiple least mean squares (LMS)-based calibrations was used to guarantee the stable operation and performance of both the QTM-PS and the DEG. The proposed RO-DPLL was fabricated in 65-nm CMOS, and it used 0.139-mm(2) silicon area and 15.67-mW power. At a fractional-N frequency near 5.2 GHz, the rms jitter and the figure of merit (FoM) of the output signal were 188 fs and -243 dB, respectively.