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A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

Cited 6 time in Web of Science Cited 4 time in Scopus
Authors

Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Choi, Jaehyouk

Issue Date
2022-02
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.2, pp.480-491
Abstract
This article presents a wide-lock-in-range and ultralow-jitter, 12-14.5 GHz subsampling phase-locked loop (SSPLL) using a frequency-disturbance-detecting/correcting (FDC) loop. By detecting and correcting the frequency disturbance, ${f_{{D}}}$ , frequently, the FDC loop can increase the lock-in range of the SSPLL to 3.2 times the reference frequency, ${f_{{REF}}}$ . Since the FDC loop only is concerned with correcting an ${f_{{D}}}$ -event at the output and is not concerned with the jitter, there is no design tradeoff between the jitter, and the power consumption as is the case in previous techniques. Due to its logic using frequency information rather than phase, the FDC loop also can reduce the time required for the reacquisition of the frequency. In this work, the prototype SSPLL was fabricated in a 65 nm CMOS, and it used the 50 MHz ${f_{{REF}}}$ . In the measurements, the FDC loop that consumed only 150 mu W of power made the SSPLL achieve the lock-in range of 160 MHz and the frequency-reacquisition time of less than 800 ns. The measured rms jitter at 13 GHz was 83 fs. The active area was 0.23 mm(2), and the total power consumption was 7.7 mW.
ISSN
0018-9200
URI
https://hdl.handle.net/10371/199379
DOI
https://doi.org/10.1109/JSSC.2021.3116149
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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