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An 82fs<sub>rms</sub>-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS

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dc.contributor.authorYoo, Seyeon-
dc.contributor.authorPark, Suneui-
dc.contributor.authorChoi, Seojin-
dc.contributor.authorCho, Yoonseo-
dc.contributor.authorYoon, Heein-
dc.contributor.authorHwang, Chanwoong-
dc.contributor.authorChoi, Jaehyouk-
dc.date.accessioned2024-04-25T04:09:51Z-
dc.date.available2024-04-25T04:09:51Z-
dc.date.created2024-04-25-
dc.date.created2024-04-25-
dc.date.issued2021-
dc.identifier.citation2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.330-+-
dc.identifier.issn0193-6530-
dc.identifier.urihttps://hdl.handle.net/10371/199387-
dc.language영어-
dc.publisherIEEE-
dc.titleAn 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS-
dc.typeArticle-
dc.identifier.doi10.1109/ISSCC42613.2021.9365956-
dc.citation.journaltitle2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)-
dc.identifier.wosid000662193600130-
dc.identifier.scopusid2-s2.0-85102360217-
dc.citation.endpage+-
dc.citation.startpage330-
dc.citation.volume64-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Jaehyouk-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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