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A-240dB-FoMjitter and-115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Yongsun | - |
| dc.contributor.author | Seong, Taeho | - |
| dc.contributor.author | Lee, Jeonghyun | - |
| dc.contributor.author | Hwang, Chanwoong | - |
| dc.contributor.author | Park, Hangi | - |
| dc.contributor.author | Choi, Jaehyouk | - |
| dc.date.accessioned | 2024-04-25T04:10:07Z | - |
| dc.date.available | 2024-04-25T04:10:07Z | - |
| dc.date.created | 2024-04-25 | - |
| dc.date.issued | 2020 | - |
| dc.identifier.citation | 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.266-+ | - |
| dc.identifier.issn | 0193-6530 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/199392 | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE | - |
| dc.title | A-240dB-FoMjitter and-115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction | - |
| dc.type | Article | - |
| dc.citation.journaltitle | 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC) | - |
| dc.identifier.wosid | 000570129800102 | - |
| dc.identifier.scopusid | 2-s2.0-85083826312 | - |
| dc.citation.endpage | + | - |
| dc.citation.startpage | 266 | - |
| dc.description.isOpenAccess | N | - |
| dc.contributor.affiliatedAuthor | Choi, Jaehyouk | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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