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A 76fs<sub>rms</sub> Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Juyeop | - |
| dc.contributor.author | Yoon, Heein | - |
| dc.contributor.author | Lim, Younghyun | - |
| dc.contributor.author | Lee, Yongsun | - |
| dc.contributor.author | Cho, Yoonseo | - |
| dc.contributor.author | Seong, Taeho | - |
| dc.contributor.author | Choi, Jaehyouk | - |
| dc.date.accessioned | 2024-04-25T04:10:34Z | - |
| dc.date.available | 2024-04-25T04:10:34Z | - |
| dc.date.created | 2024-04-25 | - |
| dc.date.issued | 2019 | - |
| dc.identifier.citation | Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.62, pp.258-+ | - |
| dc.identifier.issn | 0193-6530 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/199401 | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE | - |
| dc.title | A 76fsrms Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization | - |
| dc.type | Article | - |
| dc.citation.journaltitle | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | - |
| dc.identifier.wosid | 000463153600083 | - |
| dc.citation.endpage | + | - |
| dc.citation.startpage | 258 | - |
| dc.citation.volume | 62 | - |
| dc.description.isOpenAccess | N | - |
| dc.contributor.affiliatedAuthor | Choi, Jaehyouk | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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