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A 76fs<sub>rms</sub> Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

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dc.contributor.authorKim, Juyeop-
dc.contributor.authorYoon, Heein-
dc.contributor.authorLim, Younghyun-
dc.contributor.authorLee, Yongsun-
dc.contributor.authorCho, Yoonseo-
dc.contributor.authorSeong, Taeho-
dc.contributor.authorChoi, Jaehyouk-
dc.date.accessioned2024-04-25T04:10:34Z-
dc.date.available2024-04-25T04:10:34Z-
dc.date.created2024-04-25-
dc.date.issued2019-
dc.identifier.citationDigest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.62, pp.258-+-
dc.identifier.issn0193-6530-
dc.identifier.urihttps://hdl.handle.net/10371/199401-
dc.language영어-
dc.publisherIEEE-
dc.titleA 76fsrms Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization-
dc.typeArticle-
dc.citation.journaltitleDigest of Technical Papers - IEEE International Solid-State Circuits Conference-
dc.identifier.wosid000463153600083-
dc.citation.endpage+-
dc.citation.startpage258-
dc.citation.volume62-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Jaehyouk-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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