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A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Yongsun | - |
dc.contributor.author | Seong, Taeho | - |
dc.contributor.author | Yoo, Seyeon | - |
dc.contributor.author | Choi, Jaehyouk | - |
dc.date.accessioned | 2024-04-25T04:11:02Z | - |
dc.date.available | 2024-04-25T04:11:02Z | - |
dc.date.created | 2024-04-25 | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.307-308 | - |
dc.identifier.issn | 2153-6961 | - |
dc.identifier.uri | https://hdl.handle.net/10371/199410 | - |
dc.description.abstract | A low-jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM) is presented. Even for a high multiplication factor (i.e., 64), the proposed SLF PLL concurrently achieved ultra-low jitter and low reference spur. The prototype was fabricated in a 65-nm CMOS process. The RMS-jitter, the FOM, and the reference spur were measured as 378 fs, -242 dB, and -71 dBc, respectively. | - |
dc.language | 영어 | - |
dc.publisher | IEEE | - |
dc.title | A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique | - |
dc.type | Article | - |
dc.citation.journaltitle | 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | - |
dc.identifier.wosid | 000426987100059 | - |
dc.identifier.scopusid | 2-s2.0-85045313689 | - |
dc.citation.endpage | 308 | - |
dc.citation.startpage | 307 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Jaehyouk | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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