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A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique

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dc.contributor.authorLee, Yongsun-
dc.contributor.authorSeong, Taeho-
dc.contributor.authorYoo, Seyeon-
dc.contributor.authorChoi, Jaehyouk-
dc.date.accessioned2024-04-25T04:11:02Z-
dc.date.available2024-04-25T04:11:02Z-
dc.date.created2024-04-25-
dc.date.issued2018-
dc.identifier.citation2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.307-308-
dc.identifier.issn2153-6961-
dc.identifier.urihttps://hdl.handle.net/10371/199410-
dc.description.abstractA low-jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM) is presented. Even for a high multiplication factor (i.e., 64), the proposed SLF PLL concurrently achieved ultra-low jitter and low reference spur. The prototype was fabricated in a 65-nm CMOS process. The RMS-jitter, the FOM, and the reference spur were measured as 378 fs, -242 dB, and -71 dBc, respectively.-
dc.language영어-
dc.publisherIEEE-
dc.titleA Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique-
dc.typeArticle-
dc.citation.journaltitle2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)-
dc.identifier.wosid000426987100059-
dc.identifier.scopusid2-s2.0-85045313689-
dc.citation.endpage308-
dc.citation.startpage307-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Jaehyouk-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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