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A Wideband 180-GHz Phase-Lacked-Loop Based MSK Receiver
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Dong, S. | - |
dc.contributor.author | Momson, I. | - |
dc.contributor.author | Kshattry, S. | - |
dc.contributor.author | Yelleswarapu, P. | - |
dc.contributor.author | Choi, W. | - |
dc.contributor.author | Kenneth, K.O. | - |
dc.date.accessioned | 2024-04-30T01:21:13Z | - |
dc.date.available | 2024-04-30T01:21:13Z | - |
dc.date.created | 2024-04-26 | - |
dc.date.created | 2024-04-26 | - |
dc.date.created | 2024-04-26 | - |
dc.date.issued | 2020 | - |
dc.identifier.citation | Proceedings of the Custom Integrated Circuits Conference, Vol.2020-March | - |
dc.identifier.issn | 0886-5930 | - |
dc.identifier.uri | https://hdl.handle.net/10371/199964 | - |
dc.description.abstract | A 180 GHz mixer-first phase-locked-loop based MSK receiver is demonstrated in 65-nm CMOS. Double balanced anti-parallel-diode-pair (APDP) based sub-harmonic mixer forms the phase detector. Compensation using multiple zeros reduces the effect of in-loop delay on the stability of PLL. Without external LO synchronization, the receiver achieves 10 Gbps with a BER < 10(-12) at -24-dBm available input power. The open loop measurements show the down-conversion chain has a 3-dB bandwidth of approximately 48 GHz at 180 GHz and the minimum single side band (SSB) noise figure of 18.6 dB. This receiver is the self-synchronized receiver using coherent detection with the highest operating frequency in CMOS. This work also demonstrates that a PLL based receiver can support data rates in excess of 10 Gbps. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A Wideband 180-GHz Phase-Lacked-Loop Based MSK Receiver | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/CICC48029.2020.9075939 | - |
dc.citation.journaltitle | Proceedings of the Custom Integrated Circuits Conference | - |
dc.identifier.wosid | 000570005000068 | - |
dc.identifier.scopusid | 2-s2.0-85084521343 | - |
dc.citation.volume | 2020-March | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, W. | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | receiver | - |
dc.subject.keywordAuthor | MSK | - |
dc.subject.keywordAuthor | high speed communication | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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