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315-GHz Self-Synchronizing Minimum Shift Keying Receiver in 65-nm CMOS
Cited 1 time in
Web of Science
Cited 6 time in Scopus
- Authors
- Issue Date
- 2020
- Publisher
- IEEE
- Citation
- 2020 IEEE SYMPOSIUM ON VLSI CIRCUITS, Vol.2020-June
- Abstract
- A self-synchronizing minimum shift keying (MSK) receiver operating at 315-GHz RF is demonstrated in 65-nm CMOS. The receiver outputs digital bits and utilizes a PLL based architecture that includes a frequency doubler in the loop to achieve the 315-GHz operation. The receiver is used to form a 10-Gbps link with BER < 10(-11) at an RF input power of -21-dBm without using separate frequency synchronization between the transmitter and receiver, and data equalization. The 315-GHz RF is the highest for self-synchronizing receivers and for MSK receivers.
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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