Scalable Small-Signal Modeling of RF CMOS FET Based On 3-D EM-Based Extraction of Parasitic Effects

Abstract

An accurate scalable RF CMOS model applicable to high frequencies is developed using 3-D EM-based extraction of parasitic elements for the first time. Due to multi-metal layers, vertical interconnects, substrate loss and substrate-contact rings, the extrinsic parasitic network of CMOS FET is more complicated than GaAs FET's and does not follow, simple scaling rules. A pair of dummy patterns with different reference planes and 3-D EM simulations are sequentially used to extract the pads, vertical interconnects and extrinsic parasitic network. A new scaling rule is proposed for the layout-dependent extrinsic network parameters. A complete scalable RF CMOS model is validated by comparing the predicted and measured S-parameters of the scaled devices from a family of 0.18 mu m CMOS FET's up to 50GHz, which resulted in less than 2% error. The method is useful in choosing the optimum device geometry for a given circuit application.